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Simplified Process for Fabricating Interdigitated Energy Storage Devices

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The Technology: This simplified process for fabricating prototype IESD structures forms interlaced nano-rods of conducting material within the pores of a high-dielectric coefficient template. IESD's can be fabricated from commercially available nano-porous templates such as polycarbonate and aluminum oxide membranes or customized nano-porous templates of very high dialectric coefficient. Technology Description: Energy storage devices with large storage capability - but very small size and weight. Researchers at The University of Arizona and the University of California Irvine propose a simplified process to prepare interdigitated energy storage devices (IESD). These are compact 3-dimensional structures with superior energy densities: projected values are approximately 10000 times larger than a conventional parallel plate capacitor. IESD's contain high-surface area nano-rods of conducting material allowing for more energy storage per unit volume than a parallel plate capacitor could ever hope to achieve. Applications: 1) Pulse power demanding systems 2) Small-scale and portable electronics 3)Stand-alone sensor network device 4) Integrated Circuits (IC)


1) Large energy storage but very small physical volume versus parallel plate capacitors: significantly lesser footprint 2) Relatively simple manufacturing process envisaged: ease of scale-up for quality control and management 3) Combinations of various membrane and inclusion materials are possible for flexible device characteristics and performance

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