Methods To Efficiently Interconnect Nanoscale Computational Components With Spin-waves

Background: Design of nanoscale architectures for computing is a very new area but an important one as fundamental limits in scaling CMOS technology and power dissipation now pose significant challenges to the semiconductor industry. While there is great interest in applying nanostructures to overcoming these barriers traditional spin-based designs transmit charge which restricts the potential efficiency of interconnects and power dissipation. In order to produce effective nanoscale devices there is a need to discover new low power devices that can be interconnected efficiently and will allow scaling beyond the current barriers. Technology Description: In contrast to the charge-transmitting traditional spin-based nano-structures Spin-waves transmit waves thereby reducing the necessary power consumption and aiding in device scalability. The propagation and detection of spin-wave packets in nanostructures can be used to efficiently perform computational operations allowing for the design of the first practical fully interconnected network of processors on a single chip. Researchers at UCLA have proposed three designs utilizing spin-waves to achieve the low power device performance and improved scalability desired by leading chip manufacturers. The first device is a spin-wave-based crossbar for fully interconnecting N-inputs to N-outputs. By transmitting waves instead of traditional current transmission this novel architecture reduces power consumption and provides a high level of interconnectivity between the N paths. The second design is a reconfigurable mesh with spin-wave buses that is capable of transmitting N data over each one of the links. This innovative design will represent an original approach for nanoscale computational devices while preserving the advantages of wave-based computing. The third invention is a fully connected cluster of functional units with spin-wave buses. This invention overcomes traditional fan-in fan-out and area restrictions that prevented previous realization of a fully interconnected network in VLSI. Applications: The original designs demonstrate outstanding performance as interconnects for integrated circuit parallel components.