Engineers from UC San Diego have patented novel transistor designs having a substrate a structure supported by the substrate including a source drain gate and channel wherein the source and the channel are made of different materials and a tunnel junction formed between the source and the channel whereby the tunnel junction is configured for injecting carriers from the source to the channel. The materials used in the source and the channel are different and are chosen in order to optimize the tunneling current. Intellectual Property Info: This technology is protected by US Patent No. 8148718 and commercialization rights are available for license.
1) This invention details very low power transistors operated from a 0.3 volt or lower power supply and thresholds as low as 0.1-0.2 volts or lower and yet do not suffer from large leakage currents in the OFF state. This represents a third of the supply voltage typically utilized by modern logic transistors. Such a significant voltage reduction offers the potential for a great reduction in power consumption. Reduced power consumption is especially beneficial for portable devices that make use of exhaustible or rechargeable power supplies e.g. batteries. Reduced voltage levels are also beneficial for reducing heat generation and reducing potential interference effects between devices and interconnections between devices. 2) These new transistors are also able to turn on and off with only a small input voltage. In particular the invention provides field effect transistors that achieve subthreshold swing lower than 60 mV/decade (which is the typical limit for conventional transistors). At the same time...