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Low Swing Dual Threshold Voltage Domino Logic Circuits

Background: Domino logic circuit techniques have been extensively applied in modern high-performance microprocessors because of their superior speed and area characteristics as compared to static complementary metal oxide semiconductor (CMOS) circuits. However the domino logic gates frequently consume more dynamic switching power and display weaker noise immunity than static CMOS gates. Current aggressive circuit design which focus solely on enhancing circuit speed in microprocessors consume power levels that impose a limiting factor on system performance and functionality. Attempts to reduce power consumption by lowering the supply voltage degrade circuit speed. Recent approaches have focused on threshold voltage reduction. Compared to typical static gate a domino logic gate operates at a higher speed and occupies less area while implementing the same function. However as on-chip noise becomes more severe with technology scaling and increasing operating frequencies error free operation of domino logic circuits has become a major challenge. Technology Description: This is a domino logic circuit for microprocessors with lower power consumption than current designs without sacrificing noise immunity. It employs sleep switch transistors and a dual threshold voltage transistor distribution for placing a domino logic circuit into a low leakage state. The design offered in this invention involves a low swing domino logic circuit to reduce the power consumption. The low swing concept is also applied to the domino circuit keeper to further reduce the power consumption while enhancing speed. A simple and efficient circuit technique is proposed for dual threshold voltage implementation of the proposed low swing circuits. This leads to significant reductions in standby mode leakage power without incurring a delay penalty in the active mode as compared to completely low threshold voltage circuits. The proposed circuit reduces the leakage energy by up to 207 times as compared to standard low threshold voltage domino circuits. Applications: For CMOS microprocessor logic designs

Benefits:

1) Reduces the power consumption 2) Reduces standby mode leakage power

Date of release: