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Distributed LC Resonant Clock Trees


Background: Clock networks in high-performance designs are extremely power hungry. One potential method for reducing the power consumption is to use distributed LC tanks in which energy is conserved by shifting in between electrical and magnetic forms at the resonant frequency. Currently no physical algorithms to physically synthesize resonant trees have been proposed. Hence UCSC is the first to present an algorithm to synthesize resonant regional clock trees in ASIC’s. Technology Description: UC Santa Cruz researchers developed an algorithm which achieves significant power reduction in integrated circuits. UCSC Algorithm synthesizes resonant regional clock trees using distributed LC tanks. Algorithm allows resonant technique to be used in both ASIC and custom microprocessors. The UCSC algorithm attained a 41.7% power reduction and a modest 8.4ps skew reduction. This comes at the cost of added inductor and capacitor area but also reduces the total buffer area required.


Significant power reduction in integrated circuits.

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