Circuits Architectures And CAD Algorithms For Power Efficient FPGAs

While FPGAs are attractive design platforms due to their low cost and short time to market their power efficiencies are much lower than that of traditional ASIC designs. Currently many of the power optimization techniques proposed to overcome this problem significantly complicate the design and do not address all sources of power consumption.


1) Reduced Power Consumption (50% Reduction Observed) 2) Extremely Low Utilization Rate 3) Compatible with Traditional FPGA Layout 4) Does Not Overly Complicate the CAD Flow

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