Ultra-low-power And Robust Integrated Circuits For Logic And Memory

Background: Modern electronics manufacturers are facing numerous challenges in scaling CMOS technology into the nanoscale regime. Drain leakage increases two fold with each new technology generation; threshold voltage variation is a yield concern; fundamental thermal limits make supply-voltage scaling difficult; parasitic resistance and capacitance will seriously limit the performance of nanoscale CMOS devices. The semiconductor industry\'s solutions to these scaling problems include the adoption of thin-body MOSFET structures and the use of high- mobility channel materials. However drain leakage is still a concern in thin-body MOSFETsparticularly for gate lengths < 10nm and formation of uniformly ultra-thin (or narrow) semiconductor layers presents signficant manufacturing challenges. High-mobility channel materials present process integration challenges and do not offer dramatically enhanced performance over conventional silicon at nanometer dimensions. Technology Description: Researchers at the University of California Berkeley have developed a new device technology that overcomes the challenges of CMOS technology scaling. Zero off-state leakage excellent on-state conductance radiation-hardness and a wide operating-temperature range are just some of the features of this technology. The benefits of using the Berkeley technology include lower power consumption non-volatile operation tolerance to process variations and suitability for 3-D integration. Applications: 1) Electronics for high-temperature and high-radiation operating environments 2) Applications requiring ultra-low power consumption 3) High-density storage